Photodetectors are known in consumer and industrial electronics for detecting light and, in response thereto, generating a signal proportional thereto. For example, photodetectors have been integrated with CCD image sensors to form linear and area arrays useful in video technology. Linear CCD image sensors that achieve high speed and high photosensitivity over a wide dynamic range of light intensities are useful in applications such as laser beam profiling, acousto-optic signal processing and welding. Dynamic range is defined as the ratio of maximum to minimum detectable light intensity. The ratio is represented as either a number of orders of magnitude or in dB power. Wide dynamic range (WDR) photodetectors are those that achieve greater than 30 dB (3 orders) of dynamic range--typically 60 dB (6 orders).
The basic concept behind building a wide dynamic range photodetector is to implement a compression structure that becomes effective under high illumination conditions (&gt;30 dB where 0 dB is referenced to the minimum detectable light intensity). For lower intensity illumination (0-30 dB) the detector should operate in an integration mode for maximum sensitivity.
Additional features important to such photodetectors include a tolerance or immunity to the effects of image lag, efficiency in transferring low level signal charge (less than 100 electrons) into the readout shift register, and achievement of WDR performance at short integration times (1 to 200 .mu.s).
The basic principle behind any wide dynamic range technique is to discard a controlled portion of the total number of photogenerated electrons collected. The effect is to compress the total number of photogenerated electrons into a smaller representative charge packet that can then be transferred into the readout CCD shift register of the image sensor. Wide dynamic range typically has been achieved using one or a combination of two compression techniques: exploitation of subthreshold current flow over a barrier (described in U.S. Pat. No. 4,473,836 to Chamberlain) and signal charge partitioning based on collection well areas.
The charge partitioning compression technique is based on partitioning the collected photogenerated charge at high light levels into two components of which, the smaller one, is transferred into the readout CCD shift register. FIG. 1 shows a partitioning photodetector potential well diagram. Illumination of the `signal charge` potential well results in complete signal charge collection at low levels due to the depth of the `signal charge` potential well compared to an adjacent `excess charge` potential well. At higher light levels, photogenerated signal charge units overflow and accumulate in the `excess charge` potential well so that at the end of the integration time when the `partition gate` is turned `off`, a fraction of the total quantity of photogenerated signal charge units remains in the `signal charge` potential well for subsequent transfer into the readout CCD shift register.
With this type of detector, the amount of signal charge divided away (compression ratio) depends on the area ratios of the two potential wells. Ratios of greater than 100:1 become impractical due to layout restrictions and charge dynamics; charge dynamics for electron transfer across the `excess charge` well become prohibitively long.
U.S. Pat. No. 4,473,836 to Chamberlain, which is incorporated herein by reference, discloses an integrated wide dynamic range photodetector element for linear and area integrated circuit imaging arrays. This patent teaches a CCD image sensor technology with a photoelement for providing input power detection of a dynamic range greater than one million. The photodetector has been used successfully to form wide dynamic range CCD linear image sensor arrays.
Subsequent improvements have been made to the aforenoted photodetector, as reported in the following publications:
1. B. C. Doody and S. G. Chamberlain, "An improved wide dynamic range silicon photodetector for integration in image sensor arrays", Canadian Journal of Physics, Vol. 65, no. 8, pp. 919-923, 1987. PA1 2. S. G. Chamberlain, B. C. Doody and W. D. Washkurak, "A high photosensitivity wide dynamic range linear image sensor array", Electronic Imaging, pp. 170-175, Mar. 28-31, 1988. PA1 3. W. D. Washkurak, S. G. Chamberlain, and N. D. Prince, "High Speed wide dynamic range linear CCD detector for acousto-optic applications", SPIE Symposium and Advances in Optical Information Processing, Orlando, Fla., pp. 1-9, Apr. 4-8, 1988. PA1 q is the electron charge in coulombs, PA1 n is the quantum efficiency, PA1 H is the light intensity in watts per square cm, PA1 .lambda. is the wavelength of the incoming light in cm, PA1 h is a Planck's constant, PA1 c is the speed of light, and PA1 A is the area of the photosensitive diffusion region 2.
Although the wide dynamic range CCD photodetector discussed in the above references is capable of detecting an input power dynamic range greater than one million in commercial CCD linear image sensor arrays, the device nevertheless suffers from a number of technological limitations.
Firstly, as with other known photodetectors, the photosensitivity or NEP (noise equivalent power) of the above-discussed wide dynamic range photodetector is a function of its own capacitance.
Secondly, the above-mentioned capacitance of the photodetector also results in a slow speed of operation in the presence of short light pulses.
Thirdly, the photodetector exhibits poor photosensitivity response in the presence of short incoming light power pulses.
Finally, during the charge transfer process of the video signal into a CCD readout shift register of the photodetector, the signal may be contaminated, or smeared, by incoming incident illumination. Furthermore, blooming can also occur at high light levels.
In U.S. Pat. No. 5,235,197, granted Aug. 10, 1993 to Chamberlain and Washkurak (the inventors of the present invention), which is incorporated herein by reference, a photodetector exhibits high speed and high sensitivity detection at low light intensity and is also capable of wide dynamic range detection. In FIGS. 2A to 2C of this application, photodetector 1 is illustrated in accordance with an embodiment described in U.S. Pat. No. 5,235,197. Photodetector 1 comprises photosensitive region 2 which is in the form of an n+ diffusion into p-type semiconductor substrate 3.
In accordance with known principles of semiconductor physics, signal electrons 4 are generated within photosensitive region 2 in response to illumination of the photosensitive region by light photons of frequency defined by the photons' energy (h.nu.) as shown in the potential well diagram of FIG. 2C.
Signal electrons 4 are collected in collection well 5 which comprises a further n+ diffusion in p-type substrate 3.
Finally, signal electrons 4 are output via a CCD readout shift register comprising n-type buried layer 6 forming an active region of the shift register, transfer gate 7 of a first level polysilicon and CCD clocking gate 8 of a second level polysilicon. Transfer gate 7 and CCD clocking gate 8 are clocked via signal pulses TCK and .phi..sub.CCD, respectively.
In accordance with an aspect of this embodiment, transfer gate 9 is disposed intermediate to photosensitive region 2 and signal electron collection well 5, as will be discussed in greater detail below. Transfer gate 9 is clocked via a signal BCK.
Profiled device 10 is provided with a drain terminal connected to a source of bias voltage VPB and gate and source terminals interconnected via metalization layer 11, and further connected to the n+ collection well 5.
The combination of the n+ collection well 5 and profiled device 10 shown in FIGS. 2A and 2B relates to the wide dynamic range device described in U.S. Pat. No. 4,473,836, with the exception that collection well 5 as described herein is not a photosensitive region.
Instead, photosensitive region 2 is isolated by transfer gate 9. As shown in the potential well diagram of FIG. 2C, during integration and photocollection times, photogenerated electrons 4 initially collect in the potential well of the n+ photosensitive region 2. The signal BCK is maintained at a high level such that transfer gate 9 is open (i.e., connected as a closed circuit) and photogenerated electrons 4 are free to drift and diffuse into and collect in collection well 5. This is shown in the potential well diagram of FIG. 2C. The collection well voltage under dark conditions (i.e., no illumination of photosensitve region 2) is set to Vdn5 by means discussed below. As a result of photogenerated signal electrons collecting within collection well 5, the collection well voltage decreases (i.e., becomes more negative) in accordance with the quantity of charge units collected. The collection well voltage (Vph) changes logarithmically as a function of the light intensity incident on photosensitive region 2. The change of the collection well voltage at collection well 5 (.DELTA.Vph) is a function of the photocurrent and is given by: ##EQU1## In equation 1, K represents the responsivity of the photodetector between incident light and voltage, I.sub.dc represents the leakage current from collection well 5 and I.sub.ph represents the photocurrent from photosensitive region 2 and is given by ##EQU2##
In equation 2,
The collection well voltage at collection well 5 under dark conditions (i.e., Vdn5) is set through profiled device 10. Note that a condition at collection well equivalent to dark conditions exists when transfer gate 9 is shut off (i.e., disconnected as an open circuit). The voltage VPB is a DC bias supplied externally to device 10. The potential of photosensitive region 2 under dark conditions is set to Vdn2 by reset gate 12 and common drain bias VPR applied to drain diffusion 13. Once this potential is set, control signal voltage PR is set to zero potential, thereby isolating common drain 13 from photosensing region 2. Drain 13, gate 12, bias voltage VPR and signal voltage PR constitute a means for resetting the potential of photosensitive region 2 to Vdn2.
In operation, charge is detected and shifted out of photodetector 1 by initially applying a low logic level voltage BCK to transfer gate 9 and a high logic level voltage PR to reset gate 12 for blocking charge transfer between regions 2 and 5 while resetting the potential of photosensitive region 2 to Vdn2, as discussed above. Next, the voltage PR drops to zero potential for isolating drain region 13 from photosensitive region 2. In response to illumination, signal electrons 4 are generated within photosensitive region 2. The BCK signal goes to a high logic level so that signal electrons 4 are free to drift and diffuse into collection well 5 which, as discussed above, is preset to a potential Vdn5 (for dark conditions), Vdn5 being more positive than the potential Vdn2 of photosensitive region 2.
Next, signal electrons 4 are transferred to the CCD readout shift register 6 by alternately pulsing the TCK and .phi..sub.CCD signals applied to gates 7 and 8. See the orientation of 5, 6, 7 and 8 shown in FIG. 2A. At the same time as signal electrons 4 are being transferred to the CCD readout shift register, transfer gate 9 is disabled (i.e., disconnected as an open circuit) by applying a low logic level signal BCK thereto, for isolating photosensitive region 2 from collection well 5.
The photodetector of FIGS. 2A and 2B is characterized by two important advantages over prior photodetectors.
Firstly, the dimensions of collection well 5 can be made very small. This leads to a small node capacitance at collection well 5. A decrease in the capacitance results in a significant increase in the speed of response of the photodetector without sacrificing photosensitivity. Light pulses of width 90 nanoseconds or less can be detected at low light levels in accordance with this embodiment. In conventional wide dynamic range photodetectors, any attempt to decrease the sensing node capacitance also results in significant decreases in photosensitivity, as discussed above.
Secondly, according to the photodetector of FIGS. 2A and 2B, during charge transfer of the signal into CCD readout shift register 6, transfer gate 9 is disabled. Therefore, the signal which is stored in collection well 5 is isolated from photosensitive region 2. This ensures that the incoming light incident to photosensitive region 2 does not contaminate, smear or bloom the sampled video signal.
At the end of the integration period and after the signal charge has been transferred into readout shift register 6, photosensitive region 2 is reset to the potential VPR by enabling gate 12 in response to applying a high logic level signal PR thereto.
It is desirable to make collection well 5 even more compact and eliminate device 10 from the photodetector in order to make more compact photodetectors; however, wide dynamic range performance, high speed performance and low-light level sensitivity performance should not be sacrificed.